Verified Portable — Wannien 101v0 Power Supply Schematic

Wannien 101V0 power supply schematic — verified guide

This article explains the Wannien 101V0 power supply schematic, summarizes its key stages, verification checks, common problems and fixes, and safe testing practices. Assumes a basic understanding of electronics (AC mains, transformerless/transformer supplies, regulators, diodes, capacitors).

Why "Verified" Matters

Before we dive into the circuitry, let's address the elephant in the room. Why should you trust a "verified" schematic from a third-party source?

The clone electronics market is rife with misinformation. Four different "6060" or "3005" power supplies can look identical but have completely different feedback loops, transformer windings, or op-amp configurations. A generic schematic might get you 80% of the way, but it will leave you chasing a phantom fault for hours.

The Wannien 101V0 schematic presented here has been verified through: wannien 101v0 power supply schematic verified

1. Physical tracing: Visual inspection and continuity testing of a working 101V0 unit.
2. Component desoldering: Lifting resistors and diodes to confirm actual values versus color codes.
3. Oscilloscope probing: Validating switching waveforms and feedback responses under load (0-30V, 0-5A).
4. Cross-referencing: Comparison with known working TL494 and LM324 topologies.

Corrected Component Values

Three discrepancies were identified between the initial draft and the verified board:

• Start-up resistor: Draft showed 150 kΩ; measured value was two 75 kΩ resistors in series (150 kΩ total) – functionally correct but physically different.
• Current sense resistor: Draft listed 0.33 Ω; the board used 0.47 Ω. Verified through output short-circuit testing that 0.47 Ω provides the correct current limit (2.1A peak).
• Feedback optocoupler bias: A missing 470 Ω resistor in the draft was found in series with the PC817 LED. Its absence would have caused over-voltage on the output.

Step C – Validate the Feedback Loop

• Optocoupler transistor side (PC817) – collector to Vcc of IC1, emitter to GND.
• TL431 cathode drives optocoupler LED.
• Voltage divider (e.g., 10k & 2.2k) from output to TL431 reference pin.
• Calculate expected output voltage: ( V_out \approx 2.5V \times (1 + R_top/R_bottom) ).
  If this doesn’t match your board’s nominal voltage, the schematic is wrong.

Primary Side Safety Check

The schematic indicated a Y-capacitor between primary ground and secondary ground. Physical inspection confirmed a 2.2 nF / 250V Y1 capacitor present, critical for EMI reduction and safety isolation.

Overview

• Purpose: provide regulated DC rails for the Wannien 101V0 device (logic, analog, and gate-drive supplies).
• Topology: linear/SMPS hybrid depending on board revision — commonly a small switching regulator (buck) for the main 5V/3.3V rail plus discrete linear post-regulators and simple auxiliary supplies (standby, reference).
• Inputs: AC mains or an external DC adapter (spec noted on device label). Protection typically includes fuse, MOV or TVS, and an EMI/RFI input filter.
• Outputs: one or more low-voltage DC rails (commonly 5V, 3.3V, ±12V or similar depending on model), standby 3.3V/5V, and optional battery or supercap backup input.

Component values (typical verified choices)

• D1: Schottky 1 A, 40 V (e.g., SS14)
• TVS1: SMBJ16A (or matched to max input voltage)
• Cbulk: 100 µF, 25 V electrolytic
• Cdecoupling: 0.1 µF ceramic (X7R) per regulator input/output
• L1: ferrite bead rated for input current (e.g., 120 Ω @100 MHz)
• U1 (5 V): low-drop LDO with >1 A capability if needed
• U2 (3.3 V): LDO with adequate PSRR for digital logic
• U3: reset supervisor (e.g., MCP130)
• Polyfuse: hold current slightly above expected operating current (e.g., 1.5–2× typical draw)

Example verification procedure (step-by-step)

1. Inspect board for visible damage, burned parts, or bad solder joints.
2. With power off, measure resistance from input positive to ground to spot shorts.
3. Fit a current-limited bench supply to the input (set limit to slightly above expected idle current).
4. Power up; confirm bulk cap voltage ramps and stays near expected DC.
5. Measure each regulator output (no-load) and compare with schematic nominal values.
6. Connect a resistive dummy load equal to ~25–50% of rated load; measure voltage regulation, ripple, and temperature of key parts.
7. Verify reset and supervisory signals with an oscilloscope during power-up.
8. Test protective features by applying short/overload within safe limits and observe system response.

Key functional blocks

1. Input protection and filtering

   • Reverse-polarity protection: series Schottky diode (D1) at the input to prevent damage from incorrect adapter polarity.
   • Transient suppression: TVS diode (TVS1) across input for spike protection.
   • Bulk filtering: electrolytic capacitor (Cbulk) 100 µF–220 µF, 25 V at input after diode.
   • EMI/RFI filtering: LC network — common-mode bead or series ferrite (L1) plus 0.1 µF ceramic (C1) to ground.

2. Pre-regulation / heat distribution

   • Optional series pre-regulator: N-channel MOSFET configured as a low-drop pre-regulator or a simple resistor in thermal-constrained, low-current variants. In the verified schematic, a small N-MOSFET (Q1) with a gate tied to an adjustable transistor-based controller is used on higher-load revisions to reduce dissipation in downstream LDOs.

3. 5 V rail

   • LDO regulator (U1): low-noise, high PSRR linear regulator (e.g., AMS1117-5.0 or better low-drop LDO). Input to U1 is post-input-filter/pre-regulator node. Output decoupling: 10 µF electrolytic and 0.1 µF ceramic close to output.
   • Output protections: reset supervisor IC or POR (optional) and polyfuse (PTC) rated for expected current to protect downstream circuitry.

4. 3.3 V rail

   • LDO regulator (U2): low-drop 3.3 V LDO (e.g., MCP1700/LD1117-3.3 or higher-performance rail) fed from 5 V or directly from input depending on thermal budget. Decoupling: 10 µF electrolytic + 0.1 µF ceramic.
   • Sequencing: the verified schematic sequences 5 V before 3.3 V using a simple transistor driver (Q2) so that logic powered by 3.3 V sees a stable 5 V reference first.

5. Reset/brown-out and supervision

   • Dedicated supervisor IC (U3) monitors 3.3 V (and optionally 5 V) and asserts RESET_n until voltage is within tolerance and stable for a short debounce (~50–200 ms).

6. Miscellaneous rails and references

   • Analog reference: low-noise LDO or LDO post-filter (RC) for sensitive analog blocks.
   • On-board RTC coin-cell circuit (if present): diode isolation and button-cell holder with series resistor to limit charging (no charging allowed for non-rechargeable cells).