Verigy 93k Tester Manual ((full))

The Verigy V93000, now under the Advantest banner, stands as a cornerstone in the semiconductor industry for its revolutionary "test processor-per-pin" architecture. This essay explores the technical foundations, operational workflows, and historical evolution of this platform, which has defined high-end system-on-chip (SoC) and memory testing for over 25 years. 1. Architectural Foundations: The Test Processor-per-Pin

’s primary innovation is moving the tester intelligence directly into the test head, enabling a single scalable architecture.

Decentralized Intelligence: Unlike traditional testers that share resources across multiple pins, each pin on the Go to product viewer dialog for this item.

has its own dedicated test processor, sequencer, and timing resources. verigy 93k tester manual

Scalability: This design allows a single platform to scale from low-cost IoT devices to massive high-performance computing (HPC) and AI chips.

Modular Hardware: The system uses water-cooled building blocks to manage extreme power requirements and density, supporting up to 4096 pins. 2. Operational Framework: SmarTest Software Operating the

requires a deep understanding of its core software, SmarTest (specifically SmarTest 8), which is built on a Linux and Eclipse-based environment. The Verigy V93000, now under the Advantest banner,

Test Program Development: Engineers use SmarTest to define "test flows" and "test suites." These organize how the hardware interacts with the Device Under Test (DUT).

Debug Tools: The manual highlights critical diagnostic tools like the Shmoo plot, Margin tool, and Pattern Debugger, which allow engineers to visualize the operational limits of a chip.

Characterization: The platform excels at measuring parametric data—such as eye-width for high-speed memory or error vector magnitude (EVM) for RF transceivers—to ensure chips meet strict performance specifications. 3. Historical Context and Evolution Part 6: Common Errors & How the Manual

The V93000 was originally introduced by Hewlett-Packard (HP) in 1999.

Part 6: Common Errors & How the Manual Solves Them

| Error Message | Manual Reference | Typical Fix | |---------------|------------------|--------------| | Pin driver overcurrent | Hardware Troubleshooting -> DIB Shorts | Check DIB caps; reduce global current limit | | Pattern set mismatch | Pattern Compiler -> Link Order | Realign burst table indexes | | Calibration out of range | Service Guide -> TempComp | Run cal_tester -a with thermal chamber | | Undefined timing set | Timing Level Guide | Declare TS1 in timing.bt before use |

Introduction

The Verigy 93K tester (now owned and manufactured by Advantest as the V93000) is the gold standard for System-on-a-Chip (SoC) and high-speed memory testing in the semiconductor industry. Used by giants like Intel, AMD, Qualcomm, and TSMC, this platform handles everything from 50 MHz low-pin-count devices to 10+ Gbps high-speed SerDes interfaces.

For test engineers, product engineers, and semiconductor students, the Verigy 93K tester manual is the single most important document. However, the manual is notorious for its complexity—spanning thousands of pages across hardware, software (SmarTest), and calibration. This article breaks down everything you need to know, from locating the right documentation to mastering its core chapters.

Part 4: Core Sections of the Manual You Cannot Ignore

1. Hardware Reference Manual (Volume 1)

This section describes every physical component of the tester:

• Tester Head: The large unit that interfaces with the wafer prober or handler.
• Pin Electronics (PE): Driver, comparator, and load boards. Explains VOH, VOL, VREF, and termination.
• Power Supply Modules: PS1600, PS3200, and DPS. Includes maximum current ratings and protection circuits.
• Clock and Timing Modules (TMB, CMB): How to route system clocks to pin cards.